1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and, in particular, to the formation of lightly doped regions in a semiconductor device.
2. Description of the Related Art
The manufacturing process of integrated circuits involves the fabrication of numerous semiconductor elements on a single substrate, such as a silicon wafer. Modern integrated circuits consisting of billions of semiconductor elements, such as insulated gate field effect transistors, require a large number of complex and complicated process steps to finally complete these semiconductor elements and to electrically connect them for forming a circuitry having the desired functionality. Since critical dimensions of device features, such as the gate length of field effect transistors, are steadily decreasing to enhance integration density and improve device performance, for instance with respect to signal processing time and power consumption, each of these process steps needs to be performed with a correspondingly increasing degree of precision in order to meet the design requirements of these device features. On the other hand, for economical reasons, each process step should be carried out time-effectively to insure a high throughput and enhance productivity, thereby using the manufacturing equipment as efficiently as possible. One important process step in forming, for example, insulated gate field effect transistors that is gaining in importance when feature sizes such as the gate length of the transistor and the thickness of the gate insulation layer are reduced is the formation of lightly doped regions in a semiconductor layer. In modern field effect transistors, the thickness of the gate insulation layer separating the gate electrode from the underlying transistor active region is reduced to only a few nanometers. Moreover, the gate length of the transistor, and therefore the channel length, is steadily being scaled down, while the voltages applied to the gate, source and drain terminals of the transistor device are merely reduced to a small degree, so that the lateral electric field prevailing in the channel region of the device is increased. Consequently, charge carriers in the channel may gather sufficient energy to overcome the potential barrier between the channel and the gate insulation layer, and may therefore enter the gate insulation layer. These charge carriers may be trapped by impurity atoms and imperfections in the gate insulation layer, finally resulting in an accumulation of charge carriers in the gate insulation layer that significantly affects the electrical characteristics of a device such as the threshold voltage of the transistor. (This effect is also referred to as hot carrier effect.) This problem becomes even worse with ever-decreasing gate insulation layer thickness, since a certain amount of the charge carriers entering the gate insulation will pass the gate insulation layer and contribute to an undesired parasitic gate leakage current.
As one possibility for a solution to this problem, typically the implantation step necessary for forming doped regions for the drain and source of the transistor is divided into two or more implantation steps. In a first implantation step, dopant atoms are implanted into the transistor active region with a low dose, and in a subsequent rapid thermal annealing step, these dopant atoms are activated, i.e., diffused, to occupy lattice sites in the semiconductor lattice. Subsequently, so-called sidewall spacers are formed at sidewalls of the gate electrode so as to form a mask for a second implantation step with a high concentration of dopant atoms to obtain the required conductivity of the drain and source, respectively. In a second rapid thermal annealing step, the dopant atoms with the high concentration are also activated. As a result, drain and source regions are formed in which a smoother transition in the concentration of the dopant atoms of the drain and source regions to the inversely lightly-doped channel region is obtained. Particularly, the areas of the drain and source regions adjacent to the gate insulation layer exhibit a significantly lower dopant concentration, so that the resulting lateral electric field is reduced and the probability for charge carriers to overcome the potential barrier is decreased. For feature sizes of cutting-edge semiconductor devices, i.e., for a channel length of 0.2 xcexcm and less and for gate insulation layer thickness of 2 nm or less, a more gradual transition of the concentration is required to limit the peak intensity of the lateral electric field to an appropriate magnitude. Therefore, typically a modified implantation technique with additional implantation steps is employed to achieve a sufficient reduction of charge carrier accumulation in the gate insulation layer and a required reduction of parasitic gate leakage currents. In these additional implantation steps, a so-called halo region is formed in which the concentration of the dopant atoms decreases more gradually compared to a simple xe2x80x9ctwo-stepxe2x80x9d implantation. To obtain the halo region surrounding the lightly doped regions, typically at least one implantation step is performed with a tilt angle so as to deposit dopant atoms having a varying concentration in an area adjacent to the lightly doped region and extending beyond the gate electrode. Drain and source regions formed in the above-explained manner exhibit a gradually decreasing dopant atom concentration from the highly doped source and drain region to the lightly doped region, and to the halo regions that more or less extend beyond the gate electrode. The halo regions contact the inversely doped channel region and provide, during operation of the device, a lateral electric field with a reduced maximum intensity at the drain-gate corner of the transistor, thereby significantly reducing the probability for charge carrier injection into the gate insulation layer. In order to obtain predictable device characteristics, however, it is important to precisely control the dimensions and shape of the halo region. Accordingly, the conventional method of forming lightly doped drain and source regions not only contributes to a more complex overall process flow due to the additional implantation steps necessary for generating the halo region, but also to the complexity of the individual implantation step, since it is difficult to precisely control concentration and penetration depth of the dopant atoms which is necessary to reproducibly and reliably form the lightly doped regions. Thus, according to the typical conventional process flow requiring the complex implantation technology, the throughput, and hence the productivity, is reduced.
In view of the above, a need exists for an improved method for forming lightly doped regions in a semiconductor device, wherein the shape of a lightly doped region is precisely controllable without adversely affecting productivity of the manufacturing process.
In view of the above problems, a method of forming a lightly doped region in a semiconductor device is provided. In one illustrative embodiment, the method comprises providing a substrate comprising a semiconductor region in an upper portion thereof, forming a dielectric layer over the substrate, the dielectric layer comprising dopant atoms of the first type having a first concentration and a first diffusion length with respect to the material of the semiconductor region, and further comprising dopant atoms of a second type having a second concentration and a second diffusion length with respect to the material of the semiconductor region, and applying a predefined temperature for a predefined time period to the substrate to allow dopant atoms of the first and second type to enter the semiconductor region to create a lightly doped region in the semiconductor region with a shape and a local dopant concentration that depend on the predefined temperature, the predefined time period, the first and second concentrations, and the first and second diffusion lengths.
According to this embodiment of the present invention, two types of dopant atoms are provided in a dielectric layer which diffuse in a subsequent thermal treatment into the underlying semiconductor region. By adjusting the concentration of the two types of dopant atoms and by selecting an appropriate temperature and an appropriate time period, a required dopant distribution may be obtained due to the predefined diffusion length of these dopants.
According to a further embodiment, by patterning the dielectric layer comprising the dopant atoms, diffusion of the dopant atoms may substantially be limited to the semiconductor region underlying the dielectric layer. Thus, the present invention allows the formation of a lightly doped region having a required extension and dopant distribution with a single manufacturing step.
In a further variation, the method comprises forming a gate electrode over the semiconductor region with a gate insulation layer electrically insulating the gate electrode from the semiconductor region. By forming the gate electrode prior to the formation of the dielectric layer, the method is advantageously adaptable to the production of field effect transistors having a required doping profile without the necessity of a complex and complicated implantation step.
In a further embodiment, the gate insulation layer comprises an oxide, and the step of applying a predefined temperature for a predefined time period is performed in an oxidizing ambient to increase a thickness of the gate insulation layer at edge portions thereof. Thus, the formation of an increased corner thickness of the gate insulation layer, which is a standard procedure in a conventional process flow, can be combined with the formation of the lightly doped region so that a reduction of the overall number of process steps necessary for producing a field effect transistor is accomplished.
In a further embodiment, the dielectric layer is deposited by chemical vapor deposition, wherein the dopant atoms are added to the reaction gases so that a required concentration of the dopant atoms is obtained in the final dielectric layer by means of a well-controllable process technique. Furthermore, the dielectric layer may be patterned to form sidewall spacers for a gate electrode, eliminating the necessity for an additional process step for forming the dielectric layer including the dopant atoms.
According to another embodiment of the present invention, a method of forming a lightly doped region in a semiconductor device comprises providing a substrate comprising a semiconductor region in an upper portion thereof forming a first dielectric layer comprising dopant atoms of a first type having a first concentration and a first diffusion length with respect to the material of the semiconductor region, performing a first diffusion step by applying a predefined temperature for a predefined time period to the substrate, thereby initiating diffusion of the dopant atoms of the first type into the semiconductor region, forming a second dielectric layer comprising dopant atoms of a second type having a second concentration and a second diffusion length with respect to the material of the semiconductor region, and performing a second diffusion step applying a predefined temperature for a predefined time period to the substrate to create a lightly doped region in the semiconductor region with a shape and a local dopant concentration that depend on the first and second diffusion steps, the first and second concentrations and the first and second diffusion lengths.
Accordingly, the diffusion may be split into two separate steps which may be advantageous for adapting the present invention to a given process flow, or, for example, in case of considerably different parameters of the dopant atoms of the first and second types, such as the diffusion length, when a diffusion in a single step would not result in the desired doping profile of the lightly doped regions.
In a further variation this method comprises the formation of a gate electrode over the semiconductor region with a gate insulation layer separating the gate electrode from the semiconductor region, prior to the formation of the first dielectric layer.
In a further embodiment, the first dielectric layer is deposited in an oxidizing ambient so that the thickness of the gate insulation layer near the sidewall edges of the gate electrode is increased in the same process step. The second dielectric layer may be deposited and patterned to form sidewall spacers for the gate electrode so that the process of forming the first and second dielectric layers with the first and second types of dopant atoms is fully compatible with a standard process flow.